1. Field of the Invention
The invention relates to a method of fabricating semiconductor memory devices employing floating gates, and more particularly, to a method of fabricating memory devices employing floating gates having improved coupling ratio.
2. Description of the Prior Art
One class of semiconductor memory devices employ floating gates; that is, gates which are completely surrounded by an insulating layer, such as a silicon oxide. The presence or absence of charge in the floating gates represents binary information. These are called electrically programmable read only memories (EPROM). EEPROMS are erasable electrically programmable read only memories. "Flash" memory devices are those in which all of the cells can be erased in a single operation.
A typical high coupling ratio Flash EEPROM of the prior art, such as that described in the paper, "A High Capacitive-Coupling Ratio (HiCR) Cell for 3 V-Only 64 Mbit and Future Flash Memories," by Y. S. Hisamune et al, IEDM 93, c. 1993 by IEEE, pp. 19-22, is illustrated in FIG. 1. Gate oxide layer 42 has been grown on the surface of a semiconductor substrate 10. The tunneling oxide 46, necessary for the erase function of the cell, is grown on either side of the gate oxide layer 42 surrounding the first polysilicon layer 48. The polysilicon layer 48 is sidewall oxidized with additional tunneling oxide 50. A second polysilicon deposition is used to form spacers 52. A third polysilicon layer 54 connects the first polysilicon layer 48 and the polysilicon spacers 52 to form the floating gate of the memory cell. Interpoly dielectric layer 56 and the control gate 58 consisting of a fourth polysilicon layer complete the memory cell structure. Source and drain regions 60 are shown on either side of the gate structure. This memory cell is fabricated by a complicated process using four layers of polysilicon, an oxide/nitride capping layer, a sidewall oxidation, and two sidewall spacer etchbacks. The step height is triple polysilicon.
The paper, "A Novel Sublithographic Tunnel Diode Based 5V-Only Flash Memory," by M. Gill et al, IEDM 90, C. 1990 by IEEE, pp. 119-122, describes a memory cell having a remote tunnel diode. U.S. Pat. No. 5,278,089 to Nakagawara describes a NOR type read-only memory (ROM).